A charge pump circuit is generally used within an integrated semiconductor circuit for raising a voltage level of a power supply voltage supplied from an external circuit of the integrated semiconductor circuit and thus to obtain a required high voltage.
For instance, non-volatile memory arrays such as flash memory arrays require high positive or negative voltages to program and erase memory cells of the array. Typically, these voltages are higher than the supply voltage Vdd. Charge pumps are, therefore, used to boost on-chip voltages above the supply voltage Vdd to reach the voltages required for programming or erasing.
A charge pump circuit typically comprises cascaded stages that each pumps charges stored in a capacitor and, therefore, progressively raises the voltage levels of the intermediate nodes between the stages. Although many different circuit architectures are possible, existing bulk charge pumps are all based on this same principle that capacitors push charges from one stage to the next. Examples of conventional charge pump circuits can, for instance, be found in U.S. Pat. No. 7,098,725.
However, the body effects of the transistors in each stage, as well as the parasitic capacitances in the capacitors, degrade the performance of the conventional charge pump circuits when the number of stages is increased. In other words, the actual output voltage of the conventional charge pump circuits is lower than the ideal value because of the induced body effects.
U.S. Patent Application Publication No. US 2011/0241767 A1 discloses a charge pump circuit making use of multiple gate transistors to achieve a high level of output voltage. However, continuous efforts are made in the field of the invention to further increase the charge transfer efficiency of a charge pump circuit. Continuous efforts are also made to improve speed, to lower power dissipation and to lower area consumption of such circuit.